1. Field of the Invention
The present invention relates to a delay circuit, and more particularly, to a delay circuit having a constant period of delay, substantially independent of changes in environmental factors such as operations, temperature and voltage.
2. Description of the Related Art
With a recent trend of high-density integration and high-speed operations of semiconductor memory devices, delay circuits become more important. One of the important factors to be considered in designing a delay circuit is that there should not be a change in delay time influenced by any external environment factors. If there is a change in delay time of the delay circuit by any external factors, it may be difficult for internal circuits to perform normal operations, and internal circuits cannot operate to the maximum level of functions.
Delay circuits have been developed to be used for semiconductor memory devices. The conventional delay circuits are typically developed based on theoretical basis without taking into account external environmental influences such as temperature and voltage variations. These conventional delay circuits have problems from variations due to changes in environmental factors such as operations, temperature and voltage.
FIG. 1 illustrates a conventional delay circuit. The conventional delay circuit shown in FIG. 1 is constructed with complementary metal oxide semiconductor (CMOS) inverters. In the conventional delay circuit, if there is a change in voltage Vcc or temperature, there will be changes in the current flow through the delay circuit, making difficult for the delay circuit to have a constant period of delay time as desired.
A delay circuit having a constant period of delay time independent of changes in external environmental factors has been proposed, for example, in U.S. Pat. No. 5,453,709. FIGS. 2 through 4 illustrate the aforementioned delay circuit. FIG. 2 is a circuit diagram illustrating a conventional CMOS delay circuit having a constant period of delay time. The delay circuit includes first and second compensation circuits 1 and 2 for compensating changes in the environmental factors in the components of the delay circuit.
FIGS. 3 and 4 respectively illustrate the first and second compensation circuits 1, 2 of FIG. 2. The main principle of the delay circuit having a constant period of delay time disclosed in U.S. Pat. No. 5,453,709 is to make a period of delay time constant by using a compensation method in which the first compensation circuit 1 and second compensation circuit 2 serve to track down changes in threshold voltage and/or temperature of PMOS and NMOS transistors respectively constructed at the top/bottom ends of chains of CMOS inverters, thereby adaptively changing the current of PMOS and NMOS transistors constructed at top/bottom end of the chain of CMOS inverters.
In FIG. 3, reference symbol CE indicates a chip enabling signal, which will turn to a high state when the chip is in operation. For instance, if the threshold voltage Vth of NMOS reduces due to operational changes, current of NMOS transistor n7 increases to drop the level of an output NO. Then, voltage Vgs of NMOS transistors n14, n1, n18 and n20 (referring to FIG. 2) is reduced to compensate the reduction in the threshold voltage Vth of the transistors n14, n16, n18 and n20. In contrast, if the threshold voltage Vth increases, the level of the output NO increases to compensate the increase in the threshold voltage Vth. Also, if temperature increases, current of the transistor n7 is reduced to increase the level of the output NO. When temperature increases, the value of resistor RI increases to drop the level of the output NO. However, the reduction in the current of the transistor n7 is bigger than the increase in the resistance value of the resistor RI, so that the level of the output NO increases as temperature increases. The increase in the level of the output NO compensates the reduction in the current of the transistors n14, n16, n18 and n20 caused by the increase in temperature.
Likewise, the delay circuit is designed to have a constant period of delay time by compensating the changes caused by external environmental factors in the operational process of the second compensation circuit shown in FIG. 4, so that the delay circuit has a fixed period of delay time as disclosed in U.S. Pat. No. 5,453,709.
There is a disadvantage in the conventional delay circuit having a fixed period of delay time disclosed, for example, in U.S. Pat. No. 5,453,709 in that it is difficult to construct the delay circuit and to adjust the range of compensation in the compensation circuit using a tracking method.
It is an object of the present invention to provide a delay circuit that has a constant period of delay time by preventing a change in the delay time due to external environmental factors such as operations, temperature and voltage.
To accomplish the aforementioned and other objects of the present invention, there is provided a delay circuit having a constant delay time which includes a current source having metal oxide semiconductor (MOS) transistors of which gates are connected to each other, the current source generating a constant current by controlling sizes of the MOS transistors; and a unit delay circuit having a complementary MOS (CMOS) inverter with p-channel MOS (PMOS) transistors and n-channel MOS (NMOS) transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge or discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.
Preferably, the current source of the delay circuit includes a supply voltage being connected with respective sources of first through fourth PMOS transistors, wherein gates of the first through fourth PMOS transistors are commonly connected with an output of a comparator, a drain of the first PMOS transistor is connected with a first voltage and a diode, and a drain of the second PMOS transistor is connected with a second voltage and a resistor; the resistor being connected to diodes connected to each other in parallel having a third voltage; and the fourth PMOS transistor having a drain connected to a drain of the third PMOS transistor, wherein the constant current output from the drain of the third PMOS transistor is supplied to the unit delay circuit.
The delay circuit of the present invention may also include a current mirror for mirroring a certain level of the constant current output from the current source and for transmitting the certain level of the constant current to the non-adjacent PMOS and NMOS transistors in the unit delay circuit.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.